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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-12-30 21:07:18 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-02-17 23:44:36 +0100 |
| commit | ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8 (patch) | |
| tree | b4cd512e42e895f6ad1a2173f127af9d2df479cd /src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | |
| parent | 97e13d84c30c308c3b2bc629b38e6bcc9565dc3a (diff) | |
| download | coreboot-ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8.tar.gz coreboot-ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8.tar.bz2 coreboot-ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8.zip | |
nb/intel/x4x: Implement resume from S3 suspend
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/romstage.c')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d76fbb243484..0a1470b11252 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); |