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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
| download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.gz coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.bz2 coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.zip | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/romstage.c')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 8ba173eec644..fa69d122cb56 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -98,19 +98,6 @@ static void mb_gpio_init(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, - CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -119,7 +106,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_gpio_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |