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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-04 13:59:29 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-11 12:21:25 +0000 |
| commit | 2437fe9dfab8e4056b633a39d51d07aa81ab3c9d (patch) | |
| tree | 1dd071659a48c99c1e71ddf03b8cdf416da324c2 /src/mainboard/gigabyte/ga-g41m-es2l | |
| parent | cbe5357de02fa9f25ab9c0ca557e3057c701b059 (diff) | |
| download | coreboot-2437fe9dfab8e4056b633a39d51d07aa81ab3c9d.tar.gz coreboot-2437fe9dfab8e4056b633a39d51d07aa81ab3c9d.tar.bz2 coreboot-2437fe9dfab8e4056b633a39d51d07aa81ab3c9d.zip | |
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 989a0cb9417c..d4ce9401c12b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -96,16 +96,7 @@ static void mb_gpio_init(void) RCBA8(OIC) = 0x03; RCBA8(OIC); - RCBA32(GCS) = 0x00190464; - RCBA32(CG) = 0x00000000; - RCBA32(0x3430) = 0x00000001; - RCBA32(0x3e00) = 0xff000001; - RCBA32(0x3e08) = 0x00000080; - RCBA32(0x3e0c) = 0x00800000; - RCBA32(0x3e40) = 0xff000001; - RCBA32(0x3e48) = 0x00000080; - RCBA32(0x3e4c) = 0x00800000; - RCBA32(0x3f00) = 0x0000000b; + ich7_setup_cir(); } static void ich7_enable_lpc(void) |