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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-01 23:22:55 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:57:06 +0000 |
| commit | f9decbb0c720662d8e71fe221aef55b7ecf76196 (patch) | |
| tree | 06b2198767b4c86b7d36e7ddd6a5f56b4a1fbc54 /src/mainboard/gizmosphere/gizmo/devicetree.cb | |
| parent | e56f0c7cab77b89a750b4a3f7f380b1a10cd0d1d (diff) | |
| download | coreboot-f9decbb0c720662d8e71fe221aef55b7ecf76196.tar.gz coreboot-f9decbb0c720662d8e71fe221aef55b7ecf76196.tar.bz2 coreboot-f9decbb0c720662d8e71fe221aef55b7ecf76196.zip | |
mb/*/*: Remove AMD family14 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/gizmosphere/gizmo/devicetree.cb')
| -rw-r--r-- | src/mainboard/gizmosphere/gizmo/devicetree.cb | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb deleted file mode 100644 index f7e9a0184e55..000000000000 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ /dev/null @@ -1,53 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge - - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed - device pci 14.5 off end # USB 2 - device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector - device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex |