mb/google/asurada: revise PMIC and RTC initialization

Move the initialization from bootblock to romstage for following reasons:
- Follow MT8183 initialization sequence.
- PMIC and RTC functions are only called after verstage.
- Reduce bootblock size.
- PMIC initialization setting is complex and may need to be changed by
  an RW firmware update.

TEST=boot to kernel successfully

Change-Id: I3e4c3f918639590ffc73076450235771d06aae91
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 10 insertions, 2 deletions

diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c
index 67b43e227a1e..0f88d2022daa 100644
--- a/src/mainboard/google/asurada/romstage.c
+++ b/src/mainboard/google/asurada/romstage.c
@@ -4,12 +4,16 @@
 #include <console/console.h>
 #include <delay.h>
 #include <fmap.h>
+#include <soc/clkbuf.h>
 #include <soc/dramc_param.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
 #include <soc/pll_common.h>
+#include <soc/pmif.h>
+#include <soc/rtc.h>
+#include <soc/srclken_rc.h>
 
 /* This must be defined in chromeos.fmd in same name and size. */
 #define CALIBRATION_REGION		"RW_DDR_TRAINING"
@@ -56,8 +60,12 @@ static void raise_little_cpu_freq(void)
 
 void platform_romstage_main(void)
 {
-	mt6359p_romstage_init();
-	mt6315_romstage_init();
+	mtk_pmif_init();
+	mt6359p_init();
+	mt6315_init();
+	srclken_rc_init();
+	clk_buf_init();
+	rtc_boot();
 	raise_little_cpu_freq();
 	mt_mem_init(&dparam_ops);
 	mtk_mmu_after_dram();