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author | Marc Jones <marc.jones@se-eng.com> | 2015-06-09 14:42:55 -0600 |
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committer | Marc Jones <marc.jones@se-eng.com> | 2015-06-10 20:14:04 +0200 |
commit | 07cf24c2eefc7d6f39061bad3400a403d7879481 (patch) | |
tree | 98037054729590350a9f069660c5115aa6dfd549 /src/mainboard/google/auron/acpi_tables.c | |
parent | 36aed7474c77894ea8a3eca59991c57108d56e86 (diff) | |
download | coreboot-07cf24c2eefc7d6f39061bad3400a403d7879481.tar.gz coreboot-07cf24c2eefc7d6f39061bad3400a403d7879481.tar.bz2 coreboot-07cf24c2eefc7d6f39061bad3400a403d7879481.zip |
google/auron: Add initial mainboard copy from Peppy
Copy the Peppy directory. No changes.
Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10499
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/acpi_tables.c')
-rw-r--r-- | src/mainboard/google/auron/acpi_tables.c | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c new file mode 100644 index 000000000000..47288aa7dbc3 --- /dev/null +++ b/src/mainboard/google/auron/acpi_tables.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h> + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = CTL_TDP_SENSOR_ID; + + /* Normal TDP */ + gnvs->f1of = 0; + gnvs->f1on = 0; + + /* Limited TDP */ + gnvs->f0of = CTL_TDP_THRESHOLD_OFF; + gnvs->f0on = CTL_TDP_THRESHOLD_ON; + gnvs->f0pw = CTL_TDP_POWER_LIMIT; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + +#if CONFIG_CHROMEOS + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} |