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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 18:59:46 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-17 20:23:52 +0000 |
| commit | a3adb75b528b2e5cee1bfca84bff13f3ebe7142d (patch) | |
| tree | ba25edb376a1e6574f53368fb34b5dc1e6bb54a9 /src/mainboard/google/auron/variants/auron_yuna | |
| parent | 20cc942d9ebfb52719215d5e0b66270fc705e518 (diff) | |
| download | coreboot-a3adb75b528b2e5cee1bfca84bff13f3ebe7142d.tar.gz coreboot-a3adb75b528b2e5cee1bfca84bff13f3ebe7142d.tar.bz2 coreboot-a3adb75b528b2e5cee1bfca84bff13f3ebe7142d.zip | |
broadwell boards: Reflow USB2 parameter statements
These statements fit on a single line. Reflow them to ease future works.
Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google/auron/variants/auron_yuna')
| -rw-r--r-- | src/mainboard/google/auron/variants/auron_yuna/pei_data.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 9776bbaa1b8c..9a6fe7bcaeac 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -12,29 +12,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->dimm_channel1_disabled = 2; /* P0: LTE */ - pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, - USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL); /* P2: CCD */ - pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); /* P3: BT */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P4: Port B, CN6 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, - USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL); /* P5: EMPTY */ - pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); /* P6: SD Card */ - pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, - USB_PORT_FLEX); + pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX); /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP); /* P1: Port A, CN6 */ pei_data_usb3_port(pei_data, 0, 1, 0, 0); |