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| author | Subrata Banik <subrata.banik@intel.com> | 2019-10-30 16:48:19 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:50:03 +0000 |
| commit | 2715cdb3f32fcebdd1de6870a665a2b613c07e60 (patch) | |
| tree | 5addc7091dfc055927c7edbbb44f36a45114e77c /src/mainboard/google/beltino/dsdt.asl | |
| parent | 1e8f305957c98cb224574e1fa81938c9a692bd48 (diff) | |
| download | coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.tar.gz coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.tar.bz2 coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.zip | |
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/beltino/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/beltino/dsdt.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 41f908fcf726..7b369d8fd78d 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -53,5 +53,5 @@ DefinitionBlock( #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } |