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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-07-27 10:05:29 -0600 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-28 20:02:42 +0000 |
| commit | 17d71937a19604090258853b0856dfbe915edb0e (patch) | |
| tree | 2c05f199c07722bee180f2f1debe8de4dad14db8 /src/mainboard/google/brya/acpi | |
| parent | 1523742d4c23b3d31aac4a17b6bac7c19c8bd3b9 (diff) | |
| download | coreboot-17d71937a19604090258853b0856dfbe915edb0e.tar.gz coreboot-17d71937a19604090258853b0856dfbe915edb0e.tar.bz2 coreboot-17d71937a19604090258853b0856dfbe915edb0e.zip | |
mb/google/brya/var/agah: Optimize dGPU GCOFF entry
After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:
- Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
- Remove delay after ramping down FBVDD
This patch implements these minor changes.
BUG=b:240199017
TEST=verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/acpi')
| -rw-r--r-- | src/mainboard/google/brya/acpi/power.asl | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index e52ff8753cf5..6f69c893747e 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -174,7 +174,6 @@ Method (PGOF, 0, Serialized) /* Assert PERST# */ \_SB.PCI0.CTXS (GPIO_GPU_PERST_L) - Sleep (5) /* All rails are about to go down */ \_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG) @@ -183,7 +182,6 @@ Method (PGOF, 0, Serialized) /* Ramp down FBVDD (active-low) and let rail discharge to <10% */ \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) GPPL (GPIO_FBVDD_PG, 0, 20) - Sleep (40) /* Ramp down PEXVDD and let rail discharge to <10% */ \_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN) |