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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-08 11:00:08 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-09 18:45:00 +0000 |
| commit | 659a591aa70e2df86c4ec576b8015ac78cd1ef03 (patch) | |
| tree | 45777474d077351e767733cfbf1199e95a7aa01e /src/mainboard/google/brya/chromeos.fmd | |
| parent | 6545145f0d3cda84c0dc8a01db6ce03f6dd87832 (diff) | |
| download | coreboot-659a591aa70e2df86c4ec576b8015ac78cd1ef03.tar.gz coreboot-659a591aa70e2df86c4ec576b8015ac78cd1ef03.tar.bz2 coreboot-659a591aa70e2df86c4ec576b8015ac78cd1ef03.zip | |
mb/google/brya: Reorganize flashmap
Intel ADL-P supports an additional memory-mapped 16MiB window into the
platform SPI flash. Support for this window already exists at the SoC
level, so all that is needed is to properly organize the flash map to
take advantage of this. FW_SECTION_A moves down to the bottom of the
available space in the lower 16MiB half, and FW_SECTION_B moves to the
bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M.
BUG=b:182088676
TEST=build and boot to OS from FW_MAIN_A
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/brya/chromeos.fmd | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index 64776feee140..ad620606814a 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -1,48 +1,48 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x4ff000 +FLASH 32M { + SI_ALL 5M { + SI_DESC 4K + SI_ME } - SI_BIOS@0x500000 0x1b00000 { - # Place RW_LEGACY at the start of BIOS region such that the rest - # of BIOS regions start at 16MiB boundary. Since this is a 32MiB - # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0xb00000 - RW_SECTION_A@0xb00000 0x5e0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x32ffc0 - RW_FWID_A@0x33ffc0 0x40 - ME_RW_A(CBFS)@0x340000 0x2a0000 + SI_BIOS 27M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3M } - RW_SECTION_B@0x10e0000 0x5e0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x32ffc0 - RW_FWID_B@0x33ffc0 0x40 - ME_RW_B(CBFS)@0x340000 0x2a0000 - } - RW_MISC@0x16c0000 0x40000 { - UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 + RW_LEGACY(CBFS) 2M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 192K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 128K } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3M } # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x1700000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } |