diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-05-27 12:34:02 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-29 14:44:20 +0000 |
| commit | 5027d2de4d63359967b02ba1aecc04b8f34b1d69 (patch) | |
| tree | 8930fcc73da86c8de60ac4cd947516229e2b0085 /src/mainboard/google/brya/variants/agah/gpio.c | |
| parent | fc32b8fea3f58e41e4db869444b26ac12dcd6606 (diff) | |
| download | coreboot-5027d2de4d63359967b02ba1aecc04b8f34b1d69.tar.gz coreboot-5027d2de4d63359967b02ba1aecc04b8f34b1d69.tar.bz2 coreboot-5027d2de4d63359967b02ba1aecc04b8f34b1d69.zip | |
mb/google/brya/var/agah: Fix GPU power sequencing
While testing the power sequencing code for the GPU, a few mistakes were
found. This patch fixes those errors:
1) FBVDD load-switch enable is active-low
2) NVVDD VR enable is active-high
3) GPU_PERST_L should be driven low during GPIO table programming
4) The BAR saving code missed the top 32 bits of 64-bit BARs
5) sequence_rail() assumed the pwr_en_gpio and pg_gpio were the same
polarity
6) PEG vGPIOs were not programmed to the correct NF
BUG=b:233552225
TEST=dGPU is able to successfully enumerate over PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I85767d382012a0c7dfdb1f849768e0160f06c273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/agah/gpio.c')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/gpio.c | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index 369e373808e1..2fc965464945 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -20,7 +20,7 @@ static const struct pad_config override_gpio_table[] = { /* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */ - PAD_CFG_GPO(GPP_A19, 0, DEEP), + PAD_CFG_GPO(GPP_A19, 1, DEEP), /* A20 : DDSP_HPD2 ==> NC */ PAD_NC(GPP_A20, NONE), /* A21 : DDPC_CTRCLK ==> EN_PP3300_GPU_X */ @@ -29,7 +29,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI(GPP_A22, NONE, DEEP), /* B3 : PROC_GP2 ==> GPU_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */ PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ @@ -75,8 +75,8 @@ static const struct pad_config override_gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> NC */ PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), - /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_ODL */ - PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */ @@ -94,7 +94,7 @@ static const struct pad_config override_gpio_table[] = { /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */ PAD_CFG_GPI(GPP_E17, NONE, DEEP), /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */ - PAD_CFG_GPO(GPP_E18, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_E18, 0, LOCK_CONFIG), /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ PAD_NC(GPP_E19, NONE), /* E20 : DDP2_CTRLCLK ==> PG_PP1800_GPU_X_OD */ @@ -158,6 +158,27 @@ static const struct pad_config override_gpio_table[] = { /* S7 : SNDW3_DATA ==> SDW_HP_DATA */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; /* Early pad configuration in bootblock */ |