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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-07-27 09:56:41 -0600 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-28 20:02:24 +0000 |
| commit | 1523742d4c23b3d31aac4a17b6bac7c19c8bd3b9 (patch) | |
| tree | 0ca9258d758e2051b66f76a460c3a2ad69256dbc /src/mainboard/google/brya/variants/agah/overridetree.cb | |
| parent | d6b763ca634163c9d8b9afca51f88698704c0fa9 (diff) | |
| download | coreboot-1523742d4c23b3d31aac4a17b6bac7c19c8bd3b9.tar.gz coreboot-1523742d4c23b3d31aac4a17b6bac7c19c8bd3b9.tar.bz2 coreboot-1523742d4c23b3d31aac4a17b6bac7c19c8bd3b9.zip | |
mb/google/brya/var/agah: Update ASPM settings for dGPU
After some debugging, it has been determined that the ASPM L0s substate
is functional, but there is still some problem with ASPM L1 substates,
so this patch updates ASPM status for the dGPU from disabled to L0s
only.
BUG=b:240390998
TEST=tested with nvidia tools
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/agah/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 0f50f96712ee..ae6ad4a22dd9 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -80,7 +80,7 @@ chip soc/intel/alderlake .clk_req = 0, .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_DISABLE + .pcie_rp_aspm = ASPM_L0S, }" device pci 00.0 alias dgpu on end end |