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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-02-17 11:42:34 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-05-05 14:45:51 +0000 |
| commit | f9734fc1420a7f3fc7adde26415dfb692e15c314 (patch) | |
| tree | 4bfc351f939e0f78d3766086a811ea0621d3915e /src/mainboard/google/brya/variants/agah/overridetree.cb | |
| parent | 45789141538030777f302a9c141e9d1a4c9fbd3b (diff) | |
| download | coreboot-f9734fc1420a7f3fc7adde26415dfb692e15c314.tar.gz coreboot-f9734fc1420a7f3fc7adde26415dfb692e15c314.tar.bz2 coreboot-f9734fc1420a7f3fc7adde26415dfb692e15c314.zip | |
mb/google/brya/var/agah: Add GPU power sequencing
This patch adds support for power sequencing of the Nvidia GN3050 for
agah, which uses PCH GPIOs to control the 5 power rails required for
the GPU. The GPU is power sequenced on during mainboard
initialization, then it is enumerated on the PCI bus and its resources
are assigned. This GPU will be used in a sort of "hybrid graphics"
mode, therefore during finalization, since its PCI BARs are saved into
ACPI memory and the GPU is not required upon initial boot, the GPU is
power sequenced off.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/agah/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/overridetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index ad23f7b6f1dc..70bc09289d42 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -58,6 +58,15 @@ chip soc/intel/alderlake }" device domain 0 on + device ref pcie4_0 on + # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 alias dgpu on end + end device ref dtt on chip drivers/intel/dptf ## sensor information |