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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-07-27 10:05:29 -0600 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-28 20:02:42 +0000 |
| commit | 17d71937a19604090258853b0856dfbe915edb0e (patch) | |
| tree | 2c05f199c07722bee180f2f1debe8de4dad14db8 /src/mainboard/google/brya/variants/agah | |
| parent | 1523742d4c23b3d31aac4a17b6bac7c19c8bd3b9 (diff) | |
| download | coreboot-17d71937a19604090258853b0856dfbe915edb0e.tar.gz coreboot-17d71937a19604090258853b0856dfbe915edb0e.tar.bz2 coreboot-17d71937a19604090258853b0856dfbe915edb0e.zip | |
mb/google/brya/var/agah: Optimize dGPU GCOFF entry
After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:
- Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
- Remove delay after ramping down FBVDD
This patch implements these minor changes.
BUG=b:240199017
TEST=verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/agah')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/variant.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c index b0baab356b3a..841d2104693d 100644 --- a/src/mainboard/google/brya/variants/agah/variant.c +++ b/src/mainboard/google/brya/variants/agah/variant.c @@ -56,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = { /* In GCOFF entry order (i.e., power-off order) */ static const struct power_rail_sequence gpu_off_seq[] = { - { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 40,}, + { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 0,}, { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 10,}, { "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,}, { "NV3_3", NV33_PWR_EN, false, NV33_PG, 4,}, @@ -89,7 +89,6 @@ static void dgpu_power_sequence_off(void) { /* Assert reset and clear power-good */ gpio_output(GPU_PERST_L, 0); - mdelay(5); /* Inform the GPU that the power is no longer good. */ gpio_output(GPU_ALLRAILS_PG, 0); |