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| author | Won Chung <wonchung@google.com> | 2022-02-02 22:30:53 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-09 08:02:56 +0000 |
| commit | 9c5a10714da47f9ace52d2b35d083c7202a246af (patch) | |
| tree | 4781f49ebc5bd1bfa77cd69b173a8fdc5c9aead8 /src/mainboard/google/brya/variants/anahera/overridetree.cb | |
| parent | c5ab260cbdcf73c8c8b3e779649dd3d23039f641 (diff) | |
| download | coreboot-9c5a10714da47f9ace52d2b35d083c7202a246af.tar.gz coreboot-9c5a10714da47f9ace52d2b35d083c7202a246af.tar.bz2 coreboot-9c5a10714da47f9ace52d2b35d083c7202a246af.zip | |
mb/google/brya: Add custom PLD fields to devicetree for brya variants
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/anahera/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/overridetree.cb | 64 |
1 files changed, 56 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index e670f4a0daa1..d2b4ea14da58 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -301,13 +301,25 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(3, 1)}" device ref tcss_usb3_port3 on end end end @@ -319,19 +331,37 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(4, 2)}" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -347,7 +377,13 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(4, 1)}" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -360,13 +396,25 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(4, 1)}" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(4, 2)}" device ref usb3_port3 on end end chip drivers/usb/acpi |