diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-10-15 18:05:45 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-20 15:46:03 +0000 |
| commit | dd275f7a6c61d84da4ba743f4e0d82b7a4ebed68 (patch) | |
| tree | c66f525c3cdeeb97a98152e409ac97b643f15b29 /src/mainboard/google/brya/variants/anahera/overridetree.cb | |
| parent | cb588104263ded7b65389fff25e984636ff2d584 (diff) | |
| download | coreboot-dd275f7a6c61d84da4ba743f4e0d82b7a4ebed68.tar.gz coreboot-dd275f7a6c61d84da4ba743f4e0d82b7a4ebed68.tar.bz2 coreboot-dd275f7a6c61d84da4ba743f4e0d82b7a4ebed68.zip | |
mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMC
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6
BUG=b:197850509
TEST=build and boot into eMMC
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/anahera/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 79f7a974cb99..ad6746ebe826 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -125,7 +125,7 @@ chip soc/intel/alderlake # Enable PCIE eMMC bridge 7 using clk 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 6, - .clk_req = 2, + .clk_req = 6, .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, }" end #PCIE7 EMMC |