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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-09-30 11:32:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-01 14:57:29 +0000 |
| commit | 0d6ad2638af4aa4b6109d60da2b52fb5b9294c4b (patch) | |
| tree | dc55bec82fc831db0549b751b9832c482d7e755b /src/mainboard/google/brya/variants/felwinter | |
| parent | 6c2d99f618674f1fc0b416752ada336dafa17a15 (diff) | |
| download | coreboot-0d6ad2638af4aa4b6109d60da2b52fb5b9294c4b.tar.gz coreboot-0d6ad2638af4aa4b6109d60da2b52fb5b9294c4b.tar.bz2 coreboot-0d6ad2638af4aa4b6109d60da2b52fb5b9294c4b.zip | |
mb/google/brya/var/felwinter: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/felwinter')
| -rw-r--r-- | src/mainboard/google/brya/variants/felwinter/gpio.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index f7ad2ef5aca3..62610aced5bf 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -113,10 +113,14 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ @@ -131,6 +135,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_H13, 1, PLTRST), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -142,3 +151,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |