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| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2022-03-01 13:59:20 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-09 14:30:11 +0000 |
| commit | 6555c4c6017bcd3255611dfef36508cd8e132f65 (patch) | |
| tree | b97f8f484c49b56d7484c89d483b6e8251817743 /src/mainboard/google/brya/variants/kano/overridetree.cb | |
| parent | fadd0ff40abf37c0b030820dfb850e1b4cc6e34b (diff) | |
| download | coreboot-6555c4c6017bcd3255611dfef36508cd8e132f65.tar.gz coreboot-6555c4c6017bcd3255611dfef36508cd8e132f65.tar.bz2 coreboot-6555c4c6017bcd3255611dfef36508cd8e132f65.zip | |
mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
Based on testing results from the thermal team, they have decided
to update PL1, PL2 and PL4 for U28 SKUs.
BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/kano/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/overridetree.cb | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 5fbeb3c31dd3..39cca42b4fbc 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -63,6 +63,18 @@ chip soc/intel/alderlake }, }" + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 43, + .tdp_pl4 = 105, + }" + + register "power_limits_config[ADL_P_682_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 43, + .tdp_pl4 = 105, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -119,14 +131,14 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { .min_power = 18000, - .max_power = 28000, + .max_power = 20000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 40000, - .max_power = 40000, + .min_power = 43000, + .max_power = 43000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, |