diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-11-01 12:14:03 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-02 16:02:54 +0000 |
| commit | 67d62fdfedcfe3391bea9ad76cf64d8c472bd364 (patch) | |
| tree | b33a7925775cc946200b33d464e17790413a3ceb /src/mainboard/google/brya/variants/kano/overridetree.cb | |
| parent | 43cf27d3a7d90e07099396d2ff8af2c1435669ee (diff) | |
| download | coreboot-67d62fdfedcfe3391bea9ad76cf64d8c472bd364.tar.gz coreboot-67d62fdfedcfe3391bea9ad76cf64d8c472bd364.tar.bz2 coreboot-67d62fdfedcfe3391bea9ad76cf64d8c472bd364.zip | |
Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"
This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1.
Reason for revert: it will break s0ix.
BUG=b:201266532
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/kano/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/overridetree.cb | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index e650042549f9..899dd36f6fca 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -15,17 +15,6 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ |