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| author | Won Chung <wonchung@google.com> | 2022-05-23 22:42:39 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 04:50:49 +0000 |
| commit | c7e90a5bbe68299b54bc42041e94aa5a848e8d05 (patch) | |
| tree | 3d0123ed0a5b27111177a202f7fa110b60ad1f7a /src/mainboard/google/brya/variants/kano/overridetree.cb | |
| parent | dad64e515b1e0c01039f2dcf92b46ed270752205 (diff) | |
| download | coreboot-c7e90a5bbe68299b54bc42041e94aa5a848e8d05.tar.gz coreboot-c7e90a5bbe68299b54bc42041e94aa5a848e8d05.tar.bz2 coreboot-c7e90a5bbe68299b54bc42041e94aa5a848e8d05.zip | |
mb/google/brya/var/kano: Correct _PLD values
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
| | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I840b0f363a1ff304b310505efdaba2ac1cd10472
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/kano/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/overridetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 5962fd1a257a..ad0d0f77497e 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -443,7 +443,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -463,7 +463,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -477,7 +477,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -491,7 +491,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end |