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| author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2022-03-04 14:08:01 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-03-08 01:39:28 +0000 |
| commit | 0e834a94556854751a321d28acf20605c75aa4da (patch) | |
| tree | 4de6ae255e7a338691cab2ee7d656477b432e3fb /src/mainboard/google/brya/variants/primus | |
| parent | 42c460d3e5bd83179bfcbdc29019b1a3d2e47e9a (diff) | |
| download | coreboot-0e834a94556854751a321d28acf20605c75aa4da.tar.gz coreboot-0e834a94556854751a321d28acf20605c75aa4da.tar.bz2 coreboot-0e834a94556854751a321d28acf20605c75aa4da.zip | |
mb/google/brya/var/primus{4es}: add enable pin to rtd3-cold
Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/primus')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 36fee91a3d5d..6b8882224860 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -144,6 +144,7 @@ chip soc/intel/alderlake device ref pcie_rp3 on chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" device generic 0 alias emmc_rtd3 on end end |