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| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2022-01-12 18:16:57 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-02-14 21:12:59 +0000 |
| commit | 02b2afa8e9dacf0dfdd730902ead02580596df65 (patch) | |
| tree | 0658799465452592b00699ef93339ce725cb6445 /src/mainboard/google/brya/variants/vell/gpio.c | |
| parent | 9fc5166ca74568bf292a8f9404fd5c56cce154bf (diff) | |
| download | coreboot-02b2afa8e9dacf0dfdd730902ead02580596df65.tar.gz coreboot-02b2afa8e9dacf0dfdd730902ead02580596df65.tar.bz2 coreboot-02b2afa8e9dacf0dfdd730902ead02580596df65.zip | |
mb/google/brya/var/vell: update gpio for DMIC
Data on channel 0 & 1 are normal (from DMIC)
but there is noise on channel 2 & 3, so change to NF
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE),
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE),
BUG=b:210802722
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/vell/gpio.c')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/gpio.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index 861676d47239..e6588b9f85d8 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -66,10 +66,10 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), - /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), - /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + /* R6 : NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : NC */ + PAD_NC(GPP_R7, NONE), /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), |