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| author | Matt DeVillier <matt.devillier@gmail.com> | 2023-04-27 09:55:51 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-09 13:40:15 +0000 |
| commit | d7d74f106d7460709ca6ac069a33cf03790db293 (patch) | |
| tree | e0745c6a2dd445c48c0b730e3508d655cc3fcf18 /src/mainboard/google/brya/variants/vell/gpio.c | |
| parent | 204ffcb98d5594983aed047ec2430e0b6aa515a0 (diff) | |
| download | coreboot-d7d74f106d7460709ca6ac069a33cf03790db293.tar.gz coreboot-d7d74f106d7460709ca6ac069a33cf03790db293.tar.bz2 coreboot-d7d74f106d7460709ca6ac069a33cf03790db293.zip | |
mb/google/brya: Implement touchscreen power sequencing
For brya variants with a touchscreen, drive the enable GPIO high
starting in romstage while holding in reset, then disable the reset
GPIO in ramstage (done in the baseboard). This will allow coreboot
to detect the presence of i2c touchscreens during ACPI SSDT generation
(implemented in a subsequent commit).
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/vell/gpio.c')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/gpio.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index 90e20a68db56..54d77505292a 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -176,6 +176,12 @@ static const struct pad_config romstage_gpio_table[] = { /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* D1 : ISH_GP1 ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ |