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| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2022-05-24 15:52:54 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-30 05:21:07 +0000 |
| commit | fdfa22e5159e6f9345dbab4d431d90dd7b1a1845 (patch) | |
| tree | 4b15cdf0143c99c4efe5413cdd600f52d773f1f1 /src/mainboard/google/brya/variants/vell/gpio.c | |
| parent | 4ef61b16885322f5b89c8294ed2b49124af7b070 (diff) | |
| download | coreboot-fdfa22e5159e6f9345dbab4d431d90dd7b1a1845.tar.gz coreboot-fdfa22e5159e6f9345dbab4d431d90dd7b1a1845.tar.bz2 coreboot-fdfa22e5159e6f9345dbab4d431d90dd7b1a1845.zip | |
Revert "mb/google/brya/var/vell: Remove unused i2c7 settings"
This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9.
Reason for revert: Enable i2c7 for amp changing to 2 channel
because vell setting amp on i2c0 and i2c7 on next phase
BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
&& checks EC log and ensures the DUT could enter s0ix.
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/vell/gpio.c')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/gpio.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index a984a5a5ab4f..ed5a7070b757 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -57,10 +57,10 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), - /* H12 : Reserved I2C7_SDAL for AMP */ - PAD_NC(GPP_H12, NONE), - /* H13 : Reserved I2C7_SCL for AMP */ - PAD_NC(GPP_H13, NONE), + /* H12 : I2C7_SDA ==> PCH_I2C_AUD_L_SDA */ + PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> PCH_I2C_AUD_L_SCL */ + PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG), /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6), /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */ |