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| author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2022-09-29 11:42:19 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-02 22:03:19 +0000 |
| commit | 801f4cd9511c30aea94feebd78c724e23035f117 (patch) | |
| tree | a6805b47fd4b8ae11d95cca20f0a8a45adb2aebe /src/mainboard/google/brya/variants/xivu | |
| parent | 5b4a914fdf1124163374077e55c2e1be831cafbf (diff) | |
| download | coreboot-801f4cd9511c30aea94feebd78c724e23035f117.tar.gz coreboot-801f4cd9511c30aea94feebd78c724e23035f117.tar.bz2 coreboot-801f4cd9511c30aea94feebd78c724e23035f117.zip | |
mb/google/nissa/var/xivu: Add DPTF parameters for Xivu
The DPTF parameters were verified by the thermal team.
BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic7e0c73815dd02b97d89f94fab09a241b6279830
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/xivu')
| -rw-r--r-- | src/mainboard/google/brya/variants/xivu/overridetree.cb | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index 609f468f7356..f919cef49a6a 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -42,6 +42,57 @@ chip soc/intel/alderlake #| I2C5 | Trackpad | #+-------------------+---------------------------+ device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 77, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 78, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(TEMP_SENSOR_0, 87, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_1, 78, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 88, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" |