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| author | YH Lin <yueherngl@google.com> | 2024-01-12 01:27:40 +0000 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2024-01-22 21:42:06 +0000 |
| commit | e4fb5e7155075c2c0b2f5cdb3ba6f0f6a4d559ae (patch) | |
| tree | f82a3351bfc86156b7c166e25c48c5d7023c1cac /src/mainboard/google/brya/variants | |
| parent | 5a45ee9fb669623827306c3a3ad1eb8ccad6bfad (diff) | |
| download | coreboot-e4fb5e7155075c2c0b2f5cdb3ba6f0f6a4d559ae.tar.gz coreboot-e4fb5e7155075c2c0b2f5cdb3ba6f0f6a4d559ae.tar.bz2 coreboot-e4fb5e7155075c2c0b2f5cdb3ba6f0f6a4d559ae.zip | |
mb/google/brya: Create xol variant
Create the xol variant of the brya0 reference board by copying the
template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:319506033
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_XOL
Change-Id: Id60c50b70c9ab53d62ad48cfc15462f2410f9f02
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80145
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
6 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/xol/include/variant/ec.h b/src/mainboard/google/brya/variants/xol/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/xol/include/variant/gpio.h b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h new file mode 100644 index 000000000000..c4fe342621e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/xol/memory/Makefile.inc b/src/mainboard/google/brya/variants/xol/memory/Makefile.inc new file mode 100644 index 000000000000..eace2e443e20 --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt new file mode 100644 index 000000000000..fa247902eeee --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt new file mode 100644 index 000000000000..96211370d91b --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb new file mode 100644 index 000000000000..4f2c04a57af4 --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end |