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authorKevin Chang <kevin.chang@lcfc.corp-partner.google.com>2021-12-27 20:05:40 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-04 11:55:41 +0000
commit219bda737e5deea2b62277f453a6a853911a797a (patch)
tree847974f91d0bcdee0f5c9cf3e3d611a732a139c5 /src/mainboard/google/brya
parent8550fbcea825a8048de8dfd09d65c3b633267f40 (diff)
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mb/google/brya/var/taeko: Modify DPTF setting for taeko
The new settings from the thermal team improve performance mainly with respect to fan control settings. BRANCH=None BUG=b:212210824 TEST=Built and tested on taeko board Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
-rw-r--r--src/mainboard/google/brya/variants/taeko/overridetree.cb36
-rw-r--r--src/mainboard/google/brya/variants/taeko4es/overridetree.cb36
2 files changed, 36 insertions, 36 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 8a4538527138..79001726c2a5 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -142,31 +142,31 @@ chip soc/intel/alderlake
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
- TEMP_PCT(51, 74),
- TEMP_PCT(47, 60),
- TEMP_PCT(45, 45),
+ TEMP_PCT(50, 70),
+ TEMP_PCT(47, 58),
+ TEMP_PCT(45, 47),
TEMP_PCT(42, 45),
- TEMP_PCT(37, 35),
+ TEMP_PCT(39, 39),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
- TEMP_PCT(51, 74),
- TEMP_PCT(47, 60),
- TEMP_PCT(45, 45),
+ TEMP_PCT(50, 70),
+ TEMP_PCT(47, 58),
+ TEMP_PCT(45, 47),
TEMP_PCT(42, 45),
- TEMP_PCT(37, 35),
+ TEMP_PCT(39, 39),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
- TEMP_PCT(51, 74),
- TEMP_PCT(47, 60),
- TEMP_PCT(45, 45),
+ TEMP_PCT(50, 70),
+ TEMP_PCT(47, 58),
+ TEMP_PCT(45, 47),
TEMP_PCT(42, 45),
- TEMP_PCT(37, 35),
+ TEMP_PCT(39, 39),
}
}
}"
@@ -192,7 +192,7 @@ chip soc/intel/alderlake
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
- .max_power = 12000,
+ .max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
@@ -219,11 +219,11 @@ chip soc/intel/alderlake
[0] = { 100, 6000, 220, 2200, },
[1] = { 92, 5500, 180, 1800, },
[2] = { 85, 5000, 145, 1450, },
- [3] = { 74, 4620, 115, 1150, },
- [4] = { 60, 4290, 90, 900, },
- [5] = { 45, 3980, 55, 550, },
- [6] = { 35, 3170, 30, 300, },
- [7] = { 30, 2640, 15, 150, },
+ [3] = { 70, 4400, 115, 1150, },
+ [4] = { 56, 3900, 90, 900, },
+ [5] = { 45, 3300, 55, 550, },
+ [6] = { 38, 3000, 30, 300, },
+ [7] = { 33, 2900, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index b82e9de497fe..63566619f10a 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -138,31 +138,31 @@ chip soc/intel/alderlake
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
- TEMP_PCT(51, 74),
- TEMP_PCT(47, 60),
- TEMP_PCT(45, 45),
+ TEMP_PCT(50, 70),
+ TEMP_PCT(47, 58),
+ TEMP_PCT(45, 47),
TEMP_PCT(42, 45),
- TEMP_PCT(37, 35),
+ TEMP_PCT(39, 39),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
- TEMP_PCT(51, 74),
- TEMP_PCT(47, 60),
- TEMP_PCT(45, 45),
+ TEMP_PCT(50, 70),
+ TEMP_PCT(47, 58),
+ TEMP_PCT(45, 47),
TEMP_PCT(42, 45),
- TEMP_PCT(37, 35),
+ TEMP_PCT(39, 39),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
- TEMP_PCT(51, 74),
- TEMP_PCT(47, 60),
- TEMP_PCT(45, 45),
+ TEMP_PCT(50, 70),
+ TEMP_PCT(47, 58),
+ TEMP_PCT(45, 47),
TEMP_PCT(42, 45),
- TEMP_PCT(37, 35),
+ TEMP_PCT(39, 39),
}
}
}"
@@ -188,7 +188,7 @@ chip soc/intel/alderlake
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
- .max_power = 12000,
+ .max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
@@ -215,11 +215,11 @@ chip soc/intel/alderlake
[0] = { 100, 6000, 220, 2200, },
[1] = { 92, 5500, 180, 1800, },
[2] = { 85, 5000, 145, 1450, },
- [3] = { 74, 4620, 115, 1150, },
- [4] = { 60, 4290, 90, 900, },
- [5] = { 45, 3980, 55, 550, },
- [6] = { 35, 3170, 30, 300, },
- [7] = { 30, 2640, 15, 150, },
+ [3] = { 70, 4400, 115, 1150, },
+ [4] = { 56, 3900, 90, 900, },
+ [5] = { 45, 3300, 55, 550, },
+ [6] = { 38, 3000, 30, 300, },
+ [7] = { 33, 2900, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"