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| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2022-07-25 11:09:19 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-26 20:36:31 +0000 |
| commit | df721bd0c3ec964bc316844ed77b327a088e239d (patch) | |
| tree | dd923e1b08e2b2c6594904dbd45919a246244807 /src/mainboard/google/brya | |
| parent | 234e37099a9c742db31593cb9259e58d4fb105f9 (diff) | |
| download | coreboot-df721bd0c3ec964bc316844ed77b327a088e239d.tar.gz coreboot-df721bd0c3ec964bc316844ed77b327a088e239d.tar.bz2 coreboot-df721bd0c3ec964bc316844ed77b327a088e239d.zip | |
mb/google/brask/var/kuldax: correct Type-A USB3 port0/1 tx_de_emp
1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
signal integrity issue.
2. Disable unused USB port.
BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/kuldax/overridetree.cb | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index d31c2be69fe6..84712724f82c 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -6,6 +6,23 @@ fw_config end chip soc/intel/alderlake + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A0 + register "usb3_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A1 + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |