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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-08-11 13:42:40 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-30 15:19:06 +0000 |
| commit | 691d58f9996d2ff3820b2c08646e98f16bbde2ee (patch) | |
| tree | 043767ab2d786e0736961513a2b7d3012a5ef8ca /src/mainboard/google/butterfly/devicetree.cb | |
| parent | 6cecb0d963dd8df9440487690c11a6da75d8b70f (diff) | |
| download | coreboot-691d58f9996d2ff3820b2c08646e98f16bbde2ee.tar.gz coreboot-691d58f9996d2ff3820b2c08646e98f16bbde2ee.tar.bz2 coreboot-691d58f9996d2ff3820b2c08646e98f16bbde2ee.zip | |
nb/intel/sandybridge: Add a chipset devicetree
This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/butterfly/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index c79526e3c9b9..5ff7f9da9889 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -20,18 +20,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "666" # DDR3-1333 - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics |