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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-03 00:03:32 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 09:55:43 +0000 |
| commit | 2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2 (patch) | |
| tree | 3e4f0749bda60dd17635765faf47541eb59a4b1c /src/mainboard/google/butterfly | |
| parent | 447233ce8c25863c2236d0b208bff7f63cd738fb (diff) | |
| download | coreboot-2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2.tar.gz coreboot-2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2.tar.bz2 coreboot-2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2.zip | |
mb/**/cmos.layout: Remove crusty comments
Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/google/butterfly')
| -rw-r--r-- | src/mainboard/google/butterfly/cmos.layout | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index bee1e86fe5ed..9bd6d1b7f659 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -4,51 +4,26 @@ entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console # No serial port on this motherboard -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu # hyper_threading not supported by the Celeron 847 on this board #400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -57,8 +32,6 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 @@ -66,7 +39,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- |