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| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-04-12 12:01:48 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-04-14 00:55:47 +0000 |
| commit | 97b9d9ef246b29043cb3b6da25ae09cbc4863815 (patch) | |
| tree | edefe328b01b204ec99657ba8233277ec5dcbf9a /src/mainboard/google/cherry/devicetree.cb | |
| parent | df9549efb2649e492485a4cc2ff6c3c0b5ccc788 (diff) | |
| download | coreboot-97b9d9ef246b29043cb3b6da25ae09cbc4863815.tar.gz coreboot-97b9d9ef246b29043cb3b6da25ae09cbc4863815.tar.bz2 coreboot-97b9d9ef246b29043cb3b6da25ae09cbc4863815.zip | |
mb/google/cherry: Add MediaTek MT8195 reference board
TEST=boot from SPI-NOR and UART works fine.
Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/cherry/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/cherry/devicetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/devicetree.cb b/src/mainboard/google/cherry/devicetree.cb new file mode 100644 index 000000000000..17fccc2d291a --- /dev/null +++ b/src/mainboard/google/cherry/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8195 + device cpu_cluster 0 on + device cpu 0 on end + end +end |