mainboard/google: Add Braswell based Cyan board

Add initial files for the cyan board.
Matches chromium tree at 927026db

This board uses the Braswell FSP 1.1 image and does not build
without the FspUpdVpd.h file.

BRANCH=none
BUG=None
Test=Build and run on cyan

Change-Id: I935839be033c25e197e78fbee306104b4162a99a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10182
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 47 insertions, 0 deletions

diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
new file mode 100755
index 000000000000..0e47d35deb86
--- /dev/null
+++ b/src/mainboard/google/cyan/romstage.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <lib.h>
+#include <soc/gpio.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+/* All FSP specific code goes in this block */
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+	struct pei_data *ps = rp->pei_data;
+
+	mainboard_fill_spd_data(ps);
+
+	/* Call back into chipset code with platform values updated. */
+	romstage_common(rp);
+}
+
+void mainboard_memory_init_params(struct romstage_params *params,
+	MEMORY_INIT_UPD *memory_params)
+{
+	/* Update SPD data */
+	memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;
+	memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;
+	memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;
+}