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| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-20 14:48:57 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-15 02:36:13 +0000 |
| commit | e69a9c75816dd3cd6a9af50a09eb090ea00cfed4 (patch) | |
| tree | 63f4440d3739a1e1efe266572f3c2e8a9e7455b5 /src/mainboard/google/cyan/romstage.c | |
| parent | 982688a41ae91218fbb2cfbdb8ff19005ffce0f9 (diff) | |
| download | coreboot-e69a9c75816dd3cd6a9af50a09eb090ea00cfed4.tar.gz coreboot-e69a9c75816dd3cd6a9af50a09eb090ea00cfed4.tar.bz2 coreboot-e69a9c75816dd3cd6a9af50a09eb090ea00cfed4.zip | |
google/cyan: convert to variant configuration
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/cyan/romstage.c')
| -rw-r--r-- | src/mainboard/google/cyan/romstage.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 61ebde952990..28a8a46a39a7 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -14,13 +14,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> -#include <lib.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> #include <soc/romstage.h> -#include <string.h> /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) @@ -33,6 +27,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) romstage_common(rp); } +__attribute__ ((weak)) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { |