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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-09-29 22:06:26 -0600 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-10-09 14:44:04 +0000 |
| commit | 30b854dccd1fce2d439fb70ffa15064130cad73c (patch) | |
| tree | 1f15bf10a6d6cb35dbfeedb545f2f43b329b4fe6 /src/mainboard/google/dedede/mainboard.c | |
| parent | 9765394663f9d3b6e68b3f620dd1d429053d810c (diff) | |
| download | coreboot-30b854dccd1fce2d439fb70ffa15064130cad73c.tar.gz coreboot-30b854dccd1fce2d439fb70ffa15064130cad73c.tar.bz2 coreboot-30b854dccd1fce2d439fb70ffa15064130cad73c.zip | |
mb/google/dedede: Override GPIO PM configuration
If Cr50 is running old firmware version and hence does not ensure long
interrupt pulses, override the GPIO PM configuration.
BUG=None
TEST=Build and boot waddledee to OS. Ensure that any chip override
happens before FSP silicon parameter initialization. Ensure that the
suspend/resume sequence works fine. Ensure that the reboot sequence
works fine for 50 iterations.
Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/dedede/mainboard.c')
| -rw-r--r-- | src/mainboard/google/dedede/mainboard.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f400c6..45b25809cdc2 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,9 +4,31 @@ #include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> +#include <security/tpm/tss.h> +#include <soc/soc_chip.h> #include <vendorcode/google/chromeos/chromeos.h> +static void mainboard_update_soc_chip_config(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + int ret; + + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (!cr50_is_long_interrupt_pulse_enabled()) { + /* Disable GPIO PM to allow for shorter IRQ pulses */ + printk(BIOS_INFO, "Override GPIO PM\n"); + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + __weak void variant_isst_override(void) { /* @@ -31,6 +53,8 @@ static void mainboard_init(void *chip_info) gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + mainboard_update_soc_chip_config(); } static void mainboard_dev_init(struct device *dev) |