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| author | Felix Singer <felixsinger@posteo.net> | 2021-08-13 08:31:52 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-08-28 18:21:26 +0000 |
| commit | 0dcdb217cf4fe1d2e2055994930eda618e9fe892 (patch) | |
| tree | 7fe4277d10a93aa908cabdc591f1dfa40bca5b66 /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | 621ae7c701033029352603f2978b7580295f59e3 (diff) | |
| download | coreboot-0dcdb217cf4fe1d2e2055994930eda618e9fe892.tar.gz coreboot-0dcdb217cf4fe1d2e2055994930eda618e9fe892.tar.bz2 coreboot-0dcdb217cf4fe1d2e2055994930eda618e9fe892.zip | |
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 3a799944dd7b..857e4e144a84 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -169,11 +169,9 @@ chip soc/intel/jasperlake register "tcc_offset" = "10" # TCC of 90C - # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: # register "common_soc_config.<variable_name>" = "value" - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT # VR config settings # Imon Slope correction specified in 1/100 increment values. Range is 0-200. |