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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-07-30 09:58:27 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:25:17 +0000 |
| commit | b278838fd29fe0a0561baad23f5d306ca1374919 (patch) | |
| tree | 717e5d1dc41f753100f53f32a5b064cc92fbba33 /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | eef0152cc4ec43e25c34188628c67ce0cc59b537 (diff) | |
| download | coreboot-b278838fd29fe0a0561baad23f5d306ca1374919.tar.gz coreboot-b278838fd29fe0a0561baad23f5d306ca1374919.tar.bz2 coreboot-b278838fd29fe0a0561baad23f5d306ca1374919.zip | |
mb/google/dedede: Update CPU critical temperature
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
heavy workload like WebGL Aquarium, sometime CPU temperature spikes
till 99 degree Celsius and DPTF initiates system shutdown. This
updates CPU critical temperature trip value to 105 degree Celsius
to avoid system shutdown.
BUG=b:161993459
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: If15a873a997aa80f20940f27bbafd4498908c091
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7502489c06cc..d0609ef0cda2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -175,7 +175,7 @@ chip soc/intel/jasperlake register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 99, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" |