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| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 19:00:00 +0000 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:33:23 +0000 |
| commit | f04e83abbf98d1d55ec2c4fea3fb74bf2f459139 (patch) | |
| tree | 913e22a7f68ea646b686ea151282a9fc07048078 /src/mainboard/google/dedede/variants/baseboard/devicetree.cb | |
| parent | ad50b40eed3f7f235e848a2382ffbee6a51d1755 (diff) | |
| download | coreboot-f04e83abbf98d1d55ec2c4fea3fb74bf2f459139.tar.gz coreboot-f04e83abbf98d1d55ec2c4fea3fb74bf2f459139.tar.bz2 coreboot-f04e83abbf98d1d55ec2c4fea3fb74bf2f459139.zip | |
soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1b59ef056c6c..1349f69dab97 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -203,9 +203,6 @@ chip soc/intel/jasperlake # - PM_CFG.SLP_LAN_MIN_ASST_WDTH register "PchPmPwrCycDur" = "1" # 1s - # Enable HECI - register "HeciEnabled" = "1" - # Set xHCI LFPS period sampling off time, the default is 9ms. register "xhci_lfps_sampling_offtime_ms" = "9" |