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| author | Subrata Banik <subrata.banik@intel.com> | 2020-04-27 12:12:54 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 07:01:01 +0000 |
| commit | 38df060abad3ac105d73fc7425c89571650b40f1 (patch) | |
| tree | c1fa50cb286430177f2b2b2919f53d783ef09dbb /src/mainboard/google/dedede/variants/baseboard/gpio.c | |
| parent | 09f60ff0e259664c174070a6ed444bd3e11883c5 (diff) | |
| download | coreboot-38df060abad3ac105d73fc7425c89571650b40f1.tar.gz coreboot-38df060abad3ac105d73fc7425c89571650b40f1.tar.bz2 coreboot-38df060abad3ac105d73fc7425c89571650b40f1.zip | |
mb/google/dedede: Fix crossystem wpsw_cur error
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community
zero.
TEST=Build coreboot, flash, boot to
and log into kernel, execute "wp enable" in console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.
Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 6adb35ba9d26..1b3e015c78bc 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* C10 : GPP_C10/UART0_RTSB */ PAD_NC(GPP_C10, NONE), /* C11 : AP_WP_OD */ - PAD_NC(GPP_C11, NONE), + PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* C12 : AP_PEN_DET_ODL */ PAD_NC(GPP_C12, NONE), /* C13 : GPP_C13/UART1_TXD */ @@ -444,6 +444,8 @@ const struct pad_config *__weak variant_sleep_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) |