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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-02-11 11:53:47 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:36:16 +0000 |
| commit | 55c8702324c4ea99fe5f5a741b0c95c361f83672 (patch) | |
| tree | cc817c232a0fa91a9a94710e05e4d3b177f4f569 /src/mainboard/google/dedede/variants/baseboard/gpio.c | |
| parent | 95ea799019fdb7c0baee70bd07196910dbc0cd95 (diff) | |
| download | coreboot-55c8702324c4ea99fe5f5a741b0c95c361f83672.tar.gz coreboot-55c8702324c4ea99fe5f5a741b0c95c361f83672.tar.bz2 coreboot-55c8702324c4ea99fe5f5a741b0c95c361f83672.zip | |
mb/google/dedede: Configure I2C ports
Enable I2C ports that are used. Add GPIO configuration for the I2C
ports. Enable config items that are required for I2C HID & Generic devices.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index c334f1107a89..8e4200ab9f41 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -33,6 +33,14 @@ static const struct pad_config gpio_table[] = { /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : AP_I2C_EMR_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : AP_I2C_EMR_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART_DBG_TX_AP_RX */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART_AP_TX_DBG_RX */ @@ -41,6 +49,19 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C22, DN_20K), /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + + /* H4 : AP_I2C_TS_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : AP_I2C_TS_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : AP_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : AP_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : AP_I2C_AUDIO_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : AP_I2C_AUDIO_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ |