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| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2020-03-23 22:01:45 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:52:06 +0000 |
| commit | 9e71fdd506752391b36c518b545cf03f37351ed5 (patch) | |
| tree | de6091bbae7a47dd0b4cd4618283917a66a4c117 /src/mainboard/google/dedede/variants/baseboard/gpio.c | |
| parent | e680caa2988ee1c6b08e1ba3ed85574ca4c4da43 (diff) | |
| download | coreboot-9e71fdd506752391b36c518b545cf03f37351ed5.tar.gz coreboot-9e71fdd506752391b36c518b545cf03f37351ed5.tar.bz2 coreboot-9e71fdd506752391b36c518b545cf03f37351ed5.zip | |
mb/google/dedede: Update EC_MKBP_INT_L configuration
The concerned GPIO is configured as an open drain at the Embedded
Controller side without an external pull-up. This causes leakage in the
PP3300_A rail. So configure the GPIO to have a weak internal pull-up at
the SoC side.
BUG=b:151680590
TEST=Build the mainboard. Ensure that there are no leakages in the
PP3300_A rail.
Change-Id: I5553cf40adb92edc0fecab5c875ec8d72063ba7b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index bdc3de4f70f7..a0127370c3ec 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -127,7 +127,7 @@ static const struct pad_config gpio_table[] = { /* C14 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* C15 : EC_AP_MKBP_INT_L */ - PAD_CFG_GPI_APIC(GPP_C15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC(GPP_C15, UP_20K, PLTRST, LEVEL, INVERT), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ |