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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-06-01 17:03:41 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-07 21:46:41 +0000 |
| commit | c47422d6c3970baee5da2a9085a70bf3f987fcd5 (patch) | |
| tree | b010660433df88e3d067bee3f2bbf6e09b6dc78b /src/mainboard/google/dedede/variants/baseboard | |
| parent | 4164476dfc282c3a473d60f0f65b483086e24d50 (diff) | |
| download | coreboot-c47422d6c3970baee5da2a9085a70bf3f987fcd5.tar.gz coreboot-c47422d6c3970baee5da2a9085a70bf3f987fcd5.tar.bz2 coreboot-c47422d6c3970baee5da2a9085a70bf3f987fcd5.zip | |
soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device
This change allows treating the PMC as a 'hidden' PCI device on Jasper
Lake, so that the MMIO & I/O resources can be exposed as belonging to
this device, instead of the system agent and LPC/eSPI.
Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index a856b222c113..b5112593bc66 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -300,7 +300,7 @@ chip soc/intel/jasperlake end end # eSPI Interface device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS device pci 1f.4 off end # SMBus device pci 1f.5 on end # PCH SPI |