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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-09-11 18:51:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-22 07:02:26 +0000 |
| commit | ccbe5307d80c28953132a02dae97f0a984ffecbc (patch) | |
| tree | 5c2f35626031ccb0f92a670ab2f49a17a6cb60f0 /src/mainboard/google/dedede/variants/baseboard | |
| parent | e5655a11d21cd0b51220b11a58014c1855864075 (diff) | |
| download | coreboot-ccbe5307d80c28953132a02dae97f0a984ffecbc.tar.gz coreboot-ccbe5307d80c28953132a02dae97f0a984ffecbc.tar.bz2 coreboot-ccbe5307d80c28953132a02dae97f0a984ffecbc.zip | |
soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN
Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c23717eabc6f..1f72eb1432c1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,9 +155,6 @@ chip soc/intel/jasperlake .tdp_pl2_override = 20, }" - # Enable processor thermal control - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90C # chipset_lockdown configuration |