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| author | Teddy Shih <teddyshih@ami.corp-partner.google.com> | 2022-05-09 16:10:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-19 11:06:01 +0000 |
| commit | eb0c90aec52b1c62cd0e121940aee2375fc3f557 (patch) | |
| tree | 089bb719928d403891f94a883d5ba6dd1f700ede /src/mainboard/google/dedede/variants/beadrix/overridetree.cb | |
| parent | c2461a174da81fa2c373d4ef56747d269a0b238f (diff) | |
| download | coreboot-eb0c90aec52b1c62cd0e121940aee2375fc3f557.tar.gz coreboot-eb0c90aec52b1c62cd0e121940aee2375fc3f557.tar.bz2 coreboot-eb0c90aec52b1c62cd0e121940aee2375fc3f557.zip | |
mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE suspend
To make sure Realtek RTL8822CE suspend stress test smoothly, we remove
1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map
to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12),
as well as, remove redundant 17.0 and 1c.6 that both are described by
baseboard/devicetree.cb
BRANCH=dedede
BUG=b:230386474
TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress
test properly.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/beadrix/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/dedede/variants/beadrix/overridetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 2c82fa58915b..f811601f5780 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -130,7 +130,6 @@ chip soc/intel/jasperlake device i2c 15 on end end end # I2C 0 - device pci 17.0 off end # SATA. Baseboard/devicetree.cb is off device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -198,8 +197,6 @@ chip soc/intel/jasperlake device i2c 28 on end end end # I2C 5 - device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off - device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98360A"" |