soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 7 deletions

diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
index 5bc127dc5882..c7d6afb495a7 100644
--- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb
@@ -38,19 +38,14 @@ chip soc/intel/jasperlake
 		.tdp_pl4 = 60,
 	}"
 
-	# Enable Root Port 3 (index 2) for LAN
+	# Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
-	register "PcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "2"
 
-	# Enable Root Port 7 (index 6) for WLAN
+	# Root Port 7 (index 6) for WLAN
 	# External PCIe port 3 is mapped to PCIe Root Port 7
-	register "PcieRpEnable[6]" = "1"
 	register "PcieClkSrcUsage[3]" = "6"
 
-	# Disable PCIe Root Port 8
-	register "PcieRpEnable[7]" = "0"
-
 	# Audio related configurations
 	register "PchHdaAudioLinkDmicEnable[0]" = "0"
 	register "PchHdaAudioLinkDmicEnable[1]" = "0"