soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 2 deletions

diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 1aa2e711a975..cfaf28fbfa3e 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -7,8 +7,6 @@ fw_config
 end
 
 chip soc/intel/jasperlake
-	# Disable PCIe Root Port 8 (index 7)
-	register "PcieRpEnable[7]" = "0"
 	# Disable PCIe Clock Source 4 (index 3)
 	register "PcieClkSrcUsage[3]" = "0xff"
 
@@ -381,5 +379,6 @@ chip soc/intel/jasperlake
 				device i2c 28 on end
 			end
 		end # I2C 5
+		device pci 1c.7 off end # PCI Express Root Port 8
 	end
 end