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| author | Felix Singer <felixsinger@posteo.net> | 2021-12-05 03:13:37 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-09 22:00:23 +0000 |
| commit | 2aa1ff4eeae43869a6b6ca0036ace536915812c9 (patch) | |
| tree | 228ab8bebe78285f82aeecb22373175fe93bd1a7 /src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | |
| parent | 8474f4dc9bfd46bcb111cd3257006057b46d7f08 (diff) | |
| download | coreboot-2aa1ff4eeae43869a6b6ca0036ace536915812c9.tar.gz coreboot-2aa1ff4eeae43869a6b6ca0036ace536915812c9.tar.bz2 coreboot-2aa1ff4eeae43869a6b6ca0036ace536915812c9.zip | |
soc/intel/tigerlake: Hook up DPTF device to devicetree
Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`.
The following mainboards enable the DPTF device in the devicetree
despite `Device4Enable` is not being set.
* google/deltaur
Thus, set it to off to keep the current state unchanged.
Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/deltaur/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 643bdc1bf7b5..aeab2d4bf269 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ chip soc/intel/tigerlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF + device pci 04.0 off end # DPTF device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 |