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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-21 17:09:08 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-21 17:47:53 +0000 |
| commit | 732e9e63826f1100953b5c91259e77f4f305d6af (patch) | |
| tree | 5f5a3d40e034a323883ced665a610c6ee17f3ad4 /src/mainboard/google/drallion | |
| parent | 8b0636e06f0e5e20022baaa57625c7c8d9c1457c (diff) | |
| download | coreboot-732e9e63826f1100953b5c91259e77f4f305d6af.tar.gz coreboot-732e9e63826f1100953b5c91259e77f4f305d6af.tar.bz2 coreboot-732e9e63826f1100953b5c91259e77f4f305d6af.zip | |
mb/google/octopus: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.
The soc code gets dropped in CB:49410.
Change-Id: Ie33bae481f430a1c4410a0a4e2b2a34a3e78adaa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49411
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/drallion')
0 files changed, 0 insertions, 0 deletions