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| author | John Su <john_su@compal.corp-partner.google.com> | 2020-02-10 13:59:27 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:54:18 +0000 |
| commit | cdabc407cde7a7ccea46390b8ed0cfb7b95c826b (patch) | |
| tree | 3a956858d8618a533e8588ad73e578e10bbd55ca /src/mainboard/google/drallion | |
| parent | 99e54fece3d6e03b21366f6415dea6972a7eda8d (diff) | |
| download | coreboot-cdabc407cde7a7ccea46390b8ed0cfb7b95c826b.tar.gz coreboot-cdabc407cde7a7ccea46390b8ed0cfb7b95c826b.tar.bz2 coreboot-cdabc407cde7a7ccea46390b8ed0cfb7b95c826b.zip | |
mb/google/drallion: Set cpu_pl2_4_cfg to baseline for Drallion
Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg.
BUG=b:148912093
BRANCH=None
TEST=build coreboot and checked IA_TDC from TAT tool.
Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/drallion')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 92f3fb977273..cdb62881730a 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -65,6 +65,9 @@ chip soc/intel/cannonlake register "PchHdaIDispCodecDisconnect" = "1" register "PchHdaAudioLinkHda" = "1" + # Select CPU PL2/PL4 config + register "cpu_pl2_4_cfg" = "baseline" + # VR Settings Configuration for 2/4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | |