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| author | Shelley Chen <shchen@chromium.org> | 2017-06-09 13:05:29 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-20 03:16:51 +0200 |
| commit | 5aa64b97db0577f4ba2e83b36fc41d33453cfb3d (patch) | |
| tree | 3e7acc2cad4203f3e314261948b786f9930bf67b /src/mainboard/google/fizz/devicetree.cb | |
| parent | db287aad2547d6bc4a710c8a511448b5ff5ebead (diff) | |
| download | coreboot-5aa64b97db0577f4ba2e83b36fc41d33453cfb3d.tar.gz coreboot-5aa64b97db0577f4ba2e83b36fc41d33453cfb3d.tar.bz2 coreboot-5aa64b97db0577f4ba2e83b36fc41d33453cfb3d.zip | |
google/fizz: Enable cr50 over SPI
By default disabled. Will need to add
FIZZ_USE_SPI_TPM config to enable.
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
CQ-DEPEND=CL:530184
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20134
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index abd5452f219e..f1d2b7731ac5 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -181,6 +181,13 @@ chip soc/intel/skylake register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM + # communication before memory is up. + register "gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" + # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR # for TPM communication before memory is up. register "i2c[1]" = "{ @@ -259,7 +266,14 @@ chip soc/intel/skylake device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 on end # GSPI #0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO |