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| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 23:20:52 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-08 16:32:41 +0000 |
| commit | e21866781f73dfa468ce5da3db7e86b39e2bb4d8 (patch) | |
| tree | ca9d46e122f902965f9f168df6db8d7b5b838f06 /src/mainboard/google/fizz/variants/baseboard/devicetree.cb | |
| parent | 4d5c4e069cb99e715d04bf238e406a008f16707d (diff) | |
| download | coreboot-e21866781f73dfa468ce5da3db7e86b39e2bb4d8.tar.gz coreboot-e21866781f73dfa468ce5da3db7e86b39e2bb4d8.tar.bz2 coreboot-e21866781f73dfa468ce5da3db7e86b39e2bb4d8.zip | |
soc/intel/skylake: Enable CIO depending on devicetree configuration
Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.
Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/fizz/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e8412d5ce015..5faf760ac926 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -73,7 +73,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -376,6 +375,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 on end # I2C #2 |